Power transistors, for example, field-effect transistors, bipolar transistors, respectively IGBTs (insulated gate bipolar transistors) are electronic semiconductor components for switching or controlling high voltages, currents, respectively output power. They act as electrical resistance, which, with the aid of a control signal, can modify the current of a useful signal by several orders of magnitude. For field-effect transistors, the control signal thereby corresponds to a voltage at the gate, whereas bipolar transistors are controlled by a current at the base.
The present invention is explained in the following with reference to an FET power transistor (FE stands for field effect), which likewise applies to bipolar transistors, respectively IGBTs (insulated gate bipolar transistors), a combination of bipolar transistor and controlling field-effect transistor.
FET power transistors are used, for example, as integrated drivers for the automotive sector, for instance, as drivers for brake valves and injectors. Other applications in the automotive sector include drivers for transmitters, for example, for a parking assist system and for the pulse width-modulated energization of PTC resistors—configured lamp drivers. However, FET power transistors are also used outside of the automotive sector.
An example of an application of FET power transistors in the automotive sector is the use as a low-side switch, thus as a switch on the ground side, for controlling cyclically inductive loads, as occur, for example, in valve driver applications for application-specific integrated circuits (ASIC: application-specific integrated circuit), respectively for a vehicle dynamics control (ESP for an electronic stability program) or an anti-lock braking system (ABS). There are typically switching pulses, which are also referred to as clamped switching of an inductive load (CIS: clamped inductive switching) or also as repeated power pulses (RPP: repetitive power pulsing). Comparable events involving repeated pulse loading can also occur in the case of transistors for controlling smaller loads, respectively ohmic loads when fault conditions occur and must be controlled.
As a function of the operating point thereof, i.e., of the level of the drain-source voltage and the measure of the gate-source voltage in comparison to the threshold voltage, repeated power pulses lead in FET power transistors to a conversion of power loss in the component and thus, if indicated, to a significant self-heating. Depending on the type of event and the load profile, the resulting rapid thermal cycles can constitute a significant thermomechanical loading of the actual metallization of the components.
FIG. 1 shows a specific embodiment of a low-side switch having an FET power transistor in accordance with the related art. The schematic curves of drain voltage 20, drain current 30 and temperature 40 in accordance with the related art during a switching pulse of the low-side switch are plotted therefor in FIG. 2.
The low-side switch thereby has an FET power transistor 300 and a gate drive circuit in the form of a Zener diode chain 100 between drain 320 and gate 310 of FET power transistor 300, which allow a controlled reduction of the energy stored in the load in the case that inductive load 400 is disconnected, so that the induced voltage remains within the component specifications.
In the variant of output stage 10 shown in FIG. 1, a high power pulse is obtained during the switching-off process as follows: If the induced voltage exceeds the breakdown voltage of Zener diode chain 100, the result is that gate 320 of FET transistor 300 is charged, whereby FET transistor 300 is driven above the threshold voltage thereof to exactly the point where it can discharge the induced current, so that the energy stored in inductive load 400 is reduced. Due to the high drain voltage, this operating state briefly results in a high power loss, thereby leading to a significant self-heating of the output stage. Depending on the size of the output stage and the pulse length, this heating may lead to a temperature distribution that is considerably inhomogeneous laterally, as well as vertically. Due to the greatly differing thermal expansion coefficients of the materials for circuit traces and dielectrics (for example, aluminum-copper alloy (AlCu) or copper (Cu) as circuit trace and silicon dioxide (SiO2) as an interlayer dielectric) used within the output stage metallization, the pulsed operation leads to additional thermomechanical stress. In this way, an increasing loading of the metallization structure over the lifetime of the product can occur. In the extreme case, cumulative plastic deformation of the circuit circuit traces leads to severe mechanical stress in the interlayer dielectric (ILD for: interlayer dielectric) and finally to breakage of the same. Due to plastic deformation, metal from the circuit circuit traces can subsequently penetrate the resulting crack and result in short-circuiting of the drain-source metallization, signifying component failure (see FIG. 3). In this embodiment, the described error mechanism is also referred to as temperature induced plastic metal deformation (in the following: TPMD).
To prevent failures caused by TPMD, it is necessary to limit the occurring maximum temperature and the resulting temperature gradient in the component and the thermomechanical stress correlating therewith. This is accomplished by an optimal geometric design of the FET transistor with regard to the expected load profile.
In “A Temperature-Gradient Induced Failure Mechanism in Metallization Under Fast Thermal Cycling,” IEEE Transactions on Device and Material Reliability, vol. 8, no. 3, September 2008, Tobias Smorodin et al. describe that selective provocation endurance tests lead to circularly distributed failure locations within the output stages. The failure locations are thereby correlated with the location of the maximum temperature gradient.
In “A Proposal for Early Warning Indicators to Detect Impending Metallization Failure of DMOS Transistors in Cyclic Operation,” IEEE Proc. ICMTS (Proceedings of the International Conference on Microelectronic Test Structures), March 2015, Mathias Ritter et al. discuss introducing a potential-free metal meander structure having a supercritical design into the metallization system of the FET transistor. It is composed of the identical materials and undergoes the same thermomechanical stress as the remaining metallization system. Using the meander structure, the leakage current can be detected with regard to the drain, respectively source and resistance. Both quantities are influenced by the RPP stress and can be used to draw conclusions about the state of aging of the FET transistor.